The Design – principles

As I posted before, I was thinking of using VGA for a while, but my first real breakthrough in the design was the thought that rather than just reading directly off of the chip I could read one byte off, store that in a latch, then with a 8-to-1 chip, I could read one bit at a time off of that and display it.  It meant, more importantly to me, that only three 74 series chips would be run at 25mhz, and all the others would be run at 3.125 Mhz, which meant no high-speed problems (which I read I should avoid). It also meant that my need for fast ram would be cut, and I’d have a tonne of time to do things, but I had already found and bought a fast ram chip. So with that, I devised three other principles, which I’d use in the design.

My Basic Principles;

  • TTL  and fast TTL at that, S, ACT, or F
  • Give the ram as much room as possible, but get fast SRAM
  • Simple bus management

Fast TTL

One of my biggest fears was that when it was finished, the various latencies due to propagation etc would cause some bug (Turns out this was true, but different then I expected). I didn’t have a great logic analyzer or scope, so I wanted to keep these as small as possible. Also, power and cost wasn’t going to be an issue, I wanted to not have to dance too much around delays. So I chose chips who’s delays were in the range of 1-10ns. In hind-site it seems as if didn’t really matter that much, if you have bus contention, 2-4ns is enough time to mess everything up and the design was simple enough that delays could really stack up.

Why TTL? Well, as I found, and is probably best suited for a post of its own, when looking for chips I found the most availability and speed in the TTL line. CMOS was often unavailable, it sucked reading about a great chip, then not being able to find it, or if it was available, it was surface mount and expensive.

Ram Speed

In looking at Rams, I found a really fast 12ns 256kb SRAM. VGA has a clock speed of 25.125 Mhz, which corresponds to roughly 40ns between clock cycles. I wanted RAM that was faster than one refresh, in case as I ironed out the design I needed to fall back to that. Even though my design could handle ram 10x slower, I didn’t want to be boxed into that.

Simple Bus Management

This was one of the biggest issues I had, how to communicate between the Arduino and the Card. This was my biggest shortfall as well. I thought the simplest approach was a ‘ram ready’ signal. I would send this from the card when I had enough time to expose the internal bus to the arduino. I realize now this was a big mistake, but at the time, it meant just some transceivers. The thought came to me that the SX-28 that was handling the bus availability would know when the bus would be ready, so it could signal to arduino that it was ok to send, and the arduino could just loop waiting for the signal to know it could progress to the next byte to be stored. At first I thought this could happen at the end of every scan line. But that was silly on my part, it turns out it was only really available a couple of times during the vertical refresh areas.


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